The present invention relates to an improvement in a process for fabricating a bipolar integrated circuit having capacitors.
For fabricating a bipolar integrated circuit of this type, a process as shown in FIGS. 1(A) and 1(B) is conventionally adopted. FIGS. 1(A) and 1(B) show the case wherein npn transistors and capacitors are coexistent.
N.sup.+ -type buried layers 2 are formed by selective diffusion of As or Sb on a p-type silicon substrate 1. After growing an epitaxial layer 3 of n-type that is opposite to the conductivity of the substrate 1 to a desired concentration and thickness on the silicon substrate 1, p.sup.+ -type isolation regions 4 as element isolation regions are formed to separate regions for forming npn transistors and capacitors. Thereafter, boron, an impurity of p-type, is selectively diffused in the npn transistor-forming region to form a base 5. After depositing a thick CVD-SiO.sub.2 layer 6 on the entire surface of the structure, a diffusion window is formed in the CVD-SiO.sub.2 layer 6 at the collector-forming region. After depositing phosphor silicate glass layer 7 (PSG layer 7) on the entire surface of the structure, the parts of the PSG layer 7 and the CVD-SiO.sub.2 layer 6 on the capacitor-forming region are selectively removed. An n.sup.+ -type implanted layer 8 as a lower part electrode diffusion layer of the capacitor is formed by ion implantation or with a diffusion source of POCl.sub.3 (FIG. 1(A)).
The structure is annealed in an oxygen atmosphere to diffuse phosphorus in the PSG layer 7 to the npn transistor-forming region of the n-type epitaxial layer 3 for forming an emitter 9 and a collector 10 that are n.sup.+ -type diffusion layers. Simultaneously with this, an n.sup.+ -type implanted layer of the capacitor-forming region is diffused to form a lower part electrode diffusion layer 11, and to form a thermal oxidation layer 12 as an insulation layer of the capacitor in the n-type epitaxial layer 3 exposed through the opening. Thereafter, contact holes are formed at the parts of the CVD-SiO.sub.2 layer 6 and the PSG layer 7 on the npn transistor-forming region, and at the parts of the PSG layer 7 on the emitter 9 and the collector 10. Another contact hole is formed in the thermal oxidation layer 12 of the capacitor-forming region. An Al layer as an electrode material layer is deposited on the entire surface of the structure and is patterned. Electrodes 13, 14 and 15 for the base, the emitter and the collector, respectively; a lower part electrode 16 connected to the lower part electrode diffusion layer 11 of the capacitor-forming region; and an upper part electrode 17 formed on the thermal oxidation layer 12 are formed to provide a bipolar integrated circuit (FIG. 1(B)).
With such a conventional process, however, the thermal oxidation layer 12 as the insulation layer for the capacitor is formed by annealing the epitaxial layer 3 in which an n.sup.+ -type impurity is implanted to a high concentration. The layer 12 is thus inferior in quality, promoting the formation of pinholes. This leads to short-circuiting of the lower part electrode diffusion layer 11 and the upper part electrode 17 formed respectively below and on the thermal oxidation layer 12 so that the capacitor may not be formed. Under these circumstances, the thermal oxidation layer must be made thicker for preventing the formation of pinholes therein. When the layer is made thicker, the capacitance of the capacitor is reduced and the area of the capacitor region in the integrated circuit must be made greater for obtaining a predetermined capacitance, so that the chip area must be made greater and the packaging density is disadvantageously degraded.